The present invention generally relates to a microcontroller and, more particularly, to a microcontroller that can prefetch instructions and data.
In recent years, the operating speed of microcontrollers has increased along with an increase in the operating frequency. However, the operating speed of peripheral devices such as the memory and interface connected to the microcontroller have not kept pace with that of the microcontroller. In order to improve the processing speed of the entire system, the microcontroller includes a cache memory. However, if data is not found in the cache memory, the data must be transferred to the cache memory from a main memory of the microcontroller. During data transfer, an instruction execution unit of the microcontroller enters the wait state. As a result, the processing speed of the microcontroller is reduced. In particular, when many instructions such as branch instructions are used, the mishit ratio of the cache memory increases, and the processing speed is reduced considerably.
Japan Unexamined Patent Publication No. 3-191427 discloses a microcontroller equipped with a FIFO (first-in-first-out) memory, which is provided between the cache memory and the instruction execution unit. The FIFO memory stores an instruction supplied from the cache memory to the instruction execution unit. The instruction execution unit checks prior to processing whether the instruction stored in the FIFO memory is a branch instruction. The instruction execution unit compares the branch destination address and the tag information of the cache memory when the branch instruction is identified. If the comparison does not produce a match, the instruction execution unit transfers the data group of the main memory referenced according to the branch destination address to the cache memory. By prechecking the instruction, the instruction of the branch destination is stored in the cache memory before the instruction execution unit executes the branch instruction. Accordingly, the mishit ratio of the cache memory is reduced.
However, in order to check the branch instruction, a read circuit, a decoder, and a circuit for generating the branch destination address of the branch instruction are necessary.
Since these circuits have a complicated circuit configuration akin to the instruction execution unit, the circuit area is increased. Further, when the processing of the instruction execution unit is relatively fast, the instructions stored sequentially in the FIFO memory are transferred quickly to the instruction execution unit. Accordingly, storage of the instruction of the branch destination in the cache memory before the processing of the instruction execution unit is delayed. The microcontroller prechecks the branch instruction and prepares the instruction of the branch destination in the cache memory. However, data is not prepared previously in the cache memory. In other words, the aforementioned microcontroller does not support data prefetch.
It is an object of the present invention to provide a microcontroller having improved processing speed and a decreased mishit ratio of instructions and data.